Details : KVR1333D3N9K3/6G
triple-channel kit of three 256M x 64-bit 2GB (2048MB) DDR3-1333 CL9 SDRAM (Synchronous DRAM) memory modules, based on sixteen 128Mx 8-bit DDR3-1333 FBGA components per module. Total kit capacity is 6GB (6144MB). The SPDs are programmed to JEDEC standard latency 1333Mhztiming of 9-9-9 at 1.5V. Each 240-pin DIMM uses gold contactfingers and requires +1.5V
Specifications
JEDEC standard 1.5V ± 0.075V Power Supply VDDQ = 1.5V ± 0.075V 667MHz fCK for 1333Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 6,7,8,9 Posted CAS Programmable Additive Latency:0, CL - 2, or CL - 1 clock Programmable CAS Write Latency(CWL) = 9(DDR3-1333) 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS] Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE . 95°C Asynchronous Reset PCB : Height 1.180” (30.00mm),double sided component
This document and other documents provided pursuant are for informational purposesonly. The information type should not be interpreted to be a commitment on the part ofthe Supplier. The Supplier cannot guarantee the accuracy of information presented. The user assumes the entire risk as to the accuracy and the useof this document.